The present invention relates, in general, to transistors and, more particularly, to high frequency bipolar transistors.
Transistors having a bandwidth greater that two gigaHertz (gHz) are commonly used for communication circuits such as cellular phones and pagers. In general, communications circuits include a discrete input stage, often referred to as a "front end", coupled to integrated circuitry. The input stage receives a transmitted radio frequency or microwave frequency signal and reduces the frequency of the received signal to a level that can processed by the integrated circuitry. To improve performance and lower the cost of the communications circuits, semiconductor manufacturers would prefer to build these circuits in a single chip, thereby eliminating the need for discrete devices. However, economical solutions for manufacturing monolithically integrated communications circuits have not been realized because of the cost and complexity of a high performance integrated circuit processes.
FIG. 1 is a top view of a portion of a prior art leadframe 10 having a high frequency bipolar transistor die 12 mounted thereon. High frequency bipolar transistor die 12 has a topside collector contact 13, a topside base contact 14 and a plurality of topside emitter contacts 15. Transistor die 12 is attached to a leaded flag 11 via a thermally conductive die attach material (not shown). Methods for attaching semiconductor die to leaded flags are well known to those skilled in the art.
Collector contact 13 is coupled to leadframe lead 16 via a wirebond 17 and base contact 14 is coupled to leadframe lead 18 via a wirebond 19. Similarly, the plurality of emitter contacts 15 are coupled to leaded flag 11 via wirebonds 20.
FIG. 2 is a simplified model of a prior art high frequency bipolar transistor 21 having a collector electrode 13A, a base electrode 14A, and an emitter electrode 15A. It should be understood that transistor 21 is formed in high frequency bipolar transistor die 12 shown in FIG. 1. Accordingly, collector electrode 13A is coupled to collector contact 13, base electrode 14A is coupled to base contact 14, and emitter electrode 15A is coupled to emitter contact 15. Further, inductor 17A represents the parasitic inductance of wirebond 17, inductor 19A represents the parasitic inductance of wirebond 19, and inductor 20A represents the parasitic inductance of wirebonds 20. The parasitic inductors 17A, 19A, and 20A reduce the performance of transistor 21.
The parasitic wirebond inductances coupled to the collector, base, and emitter of transistor 21 have impedances Z.sub.c, Z.sub.b, and Z.sub.e, respectively, that vary with frequency. A typical value for a wirebond inductance is approximately 0.7 nanoHenries. The inductance of the emitter wirebond affects the voltage gain (A.sub.v) of a high frequency bipolar transistor as shown by equation 1: EQU A.sub.v =gm*(1+gm*Z.sub.e).sup.-1 (1)
where gm is the transconductance of transistor 21.
The noise figure corresponds to the input impedance of transistor 21. In general, the emitter resistance and the emitter inductance dominates the input impedance. In the hybrid-.pi. model, an emitter resistance corresponding to a transistor thermal voltage and a wirebond inductance are reflected back through the base of the bipolar transistor to its input. An approximation of the input resistance (R.sub.in) is shown in equation 2: EQU R.sub.in =.beta.*(r.sub.e +1/Ze) (2)
where r.sub.e is the emitter resistance multiplied by the transistor current gain, beta (.beta.).
The impedance Z.sub.e increases the input resistance, R.sub.in, with increasing frequency, thereby producing a lower signal-to-noise ratio at higher frequencies.
Accordingly, it would be advantageous to have a transistor capable of operating in the radio and microwave frequency ranges, have an increased gain, and have an improved noise figure. It would be of further advantage to be able to manufacture the transistor using processes capable of manufacturing high performance integrated circuits. In addition, it is desirable to lower the cost of manufacturing the transistor and packaging the transistor.